As a technique relating to a pulse generation circuit, for example, a pulse generation circuit is known which includes a delay circuit connected in a cascade, a plurality of first logic circuits connected to an output of the delay circuit generating pulses each having a time width corresponding to a delay amount per stage of the delay circuit, and a second logic circuit that obtains a logical sum of the outputs of the plurality of first logic circuits.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication No. 2007-228546.